Add first draft of spec
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spec.tex
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spec.tex
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\documentclass[a4paper]{article}
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\usepackage{array}
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\usepackage{graphicx}
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\usepackage[utf8]{inputenc}
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\usepackage{multirow}
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\usepackage{nameref}
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\usepackage{parskip}
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\usepackage{tabularx}
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\newcolumntype{B}{>{\centering\tiny\bfseries\arraybackslash}X}
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\newcommand{\noopcode}{\multicolumn{1}{c|}{--}}
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\newcommand{\op}[1]{\texttt{#1}}
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\newcommand{\opsep}{\cline{2-8} \multicolumn{1}{|c|}{}}
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\newcommand{\opfamily}[2]{
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\hline\multicolumn{1}{|c|}{\multirow{#1}{*}{\rotatebox{90}{\textbf{#2}}}}}
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\title{ETD32 ISA Specification}
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\author{Camden Dixie O'Brien}
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\begin{document}
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\maketitle
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The ETD32 ISA is a little-endian, 32-bit RISC architecture, primarily
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designed to be simple and relatively easy to implement for teaching
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processor internals and design.
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\section{Registers}
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\begin{table}[h]
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\centering
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\begin{tabularx}{\textwidth}{|l|r|X|}
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\hline
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\textbf{Name} & \textbf{Number} & \textbf{Purpose} \\
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\hline
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Z & 0 & ``Black hole'' pseudo-register \\
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\hline
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R1--R29 & 1--29 & General purpose \\
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\hline
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SP & 30 & Stack pointer \\
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\hline
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PC & 31 & Program counter \\
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\hline
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\end{tabularx}
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\caption{List of Registers}
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\end{table}
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There are a total of 32 directly addressable registers. They are
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uniquely identified by their 5-bit register number.
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In addition to these, there is a flags register which cannot be
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addressed directly, but affects conditional execution of commands; see
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section \ref{sec:conditional-execution} for more details.
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\section{Addressing Modes}
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\subsection{Register Direct (\texttt{RD})}
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\begin{center}
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\texttt{Op R\textsubscript{dest},R\textsubscript{src1},R\textsubscript{src2}}
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\end{center}
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In register direct mode, the operands consist of up to three register
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numbers. The first register is always a destination; if the second and
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third are present they are used as sources.
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\subsection{Register-Immediate (\texttt{RI})}
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\begin{center}
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\texttt{Op R\textsubscript{dest},R\textsubscript{src},\#I}
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\end{center}
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Register-immediate instructions have a destination register and a
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single source register, with the rest of the instruction being a
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signed, 12-bit immediate value.
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\subsection{Base-Offset (\texttt{BO})}
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\begin{center}
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\texttt{
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Op R\textsubscript{target},[R\textsubscript{base},\#I\textsubscript{offset}]}
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\end{center}
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Base-offset addressing uses a target register, which may be used as
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input or output depending on the operation, a base register and a
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12-bit immediate value (the offset). The offset is added to the value
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of the base register, and this is used as a memory address.
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\subsection{Base-Index (\texttt{BI})}
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\begin{center}
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\texttt{
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Op R\textsubscript{target},[R\textsubscript{base},R\textsubscript{index}]}
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\end{center}
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Base-index addressing is similar to base-offset addressing, except an
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index register is provided instead of an offset immediate. The values
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of the base and index registers are added together and used as a
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memory address.
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\subsection{Immediate-Only (\texttt{I})}
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\begin{center}
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\texttt{Op \#I}
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\end{center}
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The simplest addressing mode; immediate-only instructions specify a
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single, signed, 22-bit immediate value.
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\section{Conditional Execution}
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\label{sec:conditional-execution}
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Many instructions set the condition flags, which are stored in the
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(not directly addressable) flags register. Any flags that are not set
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by an operation are implicitly cleared.
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\begin{table}[h]
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\centering
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\begin{tabularx}{\textwidth}{|c|X|}
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\hline
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\textbf{Flag} & \textbf{Description} \\
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\hline
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C & Carry / overflow \\
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\hline
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N & Less than zero \\
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\hline
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Z & Equal to zero \\
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\hline
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P & Greater than zero \\
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\hline
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\end{tabularx}
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\caption{Condition flags}
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\label{tab:condition-flags}
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\end{table}
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All instructions can be conditionally executed depending on any
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combination of the four condition flags in the flag register. This is
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denoted by appending a question mark (`?') and the character codes of
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all flags that should be depended on to the opcode. For example, a
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suffix of \texttt{?NP} would indicate that the instruction should only
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be executed if the \texttt{N} and \texttt{P} flags are both set---that
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is, if the previous command yielded a value that was not equal to
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zero.
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\section{Operations}
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There are a total of 18 distinct operations, with 33 opcodes (each
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addressing mode variant of a command has its own opcode). They fall
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into three categories: \textbf{Logic \& Arithmetic}, \textbf{Memory}
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and \textbf{Flow Control}.
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Refer to table \ref{tab:operations} for an exhaustive list of these
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operations and their opcodes.
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\begin{table}[p]
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\begin{tabularx}{\textwidth}{cl|*{5}{r|}X|}
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\cline{3-8}
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& &
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\multicolumn{5}{c|}{\textbf{Opcode}} &
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\multirow{2}{*}{\textbf{Description}} \\
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\cline{3-7}
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&
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& \multicolumn{1}{c|}{\texttt{RD}} & \multicolumn{1}{c|}{\texttt{RI}}
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& \multicolumn{1}{c|}{\texttt{BO}} & \multicolumn{1}{c|}{\texttt{BI}}
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& \multicolumn{1}{c|}{\texttt{I}} & \\
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\opfamily{14}{Logic \& Arithmetic} &
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\op{LLS} & 0 & 1 & \noopcode & \noopcode & \noopcode &
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Applies a logical left shift to its first input; the second input
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determines the number of places \\
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\opsep &
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\op{LRS} & 2 & 3 & \noopcode & \noopcode & \noopcode &
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Logical right shift; otherwise the same as \texttt{LLS} \\
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\opsep &
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\op{AND} & 4 & 5 & \noopcode & \noopcode & \noopcode &
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Bitwise \texttt{AND}s its inputs \\
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\opsep &
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\op{OR} & 6 & 7 & \noopcode & \noopcode & \noopcode &
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Bitwise \texttt{OR}s its inputs \\
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\opsep &
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\op{XOR} & 8 & 9 & \noopcode & \noopcode & \noopcode &
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Bitwise \texttt{XOR}s its inputs \\
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\opsep &
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\op{NOT} & 10 & \noopcode & \noopcode & \noopcode & \noopcode &
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Bitwise \texttt{NOT}s its first input. The second input is ignored. \\
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\opsep &
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\op{ADD} & 11 & 12 & \noopcode & \noopcode & \noopcode &
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Adds its inputs \\
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\opsep &
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\op{SUB} & 13 & 14 & \noopcode & \noopcode & \noopcode &
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Subtracts its second input from its first (two's complement) \\
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\opsep &
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\op{MUL} & 15 & 16 & \noopcode & \noopcode & \noopcode &
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Multiplies its inputs \\
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\opfamily{10}{Memory} &
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\op{LD8} & \noopcode & \noopcode & 17 & 18 & \noopcode &
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Loads a byte from the address in memory and writes it to the
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target register \\
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\opsep & \op{LD16} & \noopcode & \noopcode & 19 & 20 & \noopcode &
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Same as \texttt{LD8}, but a half-word \\
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\opsep & \op{LD32} & \noopcode & \noopcode & 21 & 22 & \noopcode &
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Same as \texttt{LD16}, but a full word \\
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\opsep &
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\op{ST8} & \noopcode & \noopcode & 23 & 24 & \noopcode &
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Writes the least-significant byte of the contents of the target register
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to the memory address \\
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\opsep &
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\op{ST16} & \noopcode & \noopcode & 25 & 26 & \noopcode &
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Same as \texttt{ST8} but a half-word \\
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\opsep &
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\op{ST16} & \noopcode & \noopcode & 27 & 28 & \noopcode &
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Same as \texttt{ST8} but a full word \\
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\opfamily{7}{Flow control} &
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\op{B} & \noopcode & \noopcode & \noopcode & \noopcode & 29 &
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Jump to the given offset from the PC; argument must be a multiple of 4 \\
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\opsep &
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\op{JMP} & 30 & \noopcode & \noopcode & \noopcode & 31 &
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Jump to the given address; must be word-aligned. For the \texttt{RD}
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variant, only the first source register is used. \\
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\opsep &
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\op{TI} & \noopcode & \noopcode & \noopcode & \noopcode & 32 &
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Trigger a software interrupt; the argument is ignored \\
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\hline
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\end{tabularx}
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\caption{List of Operations}
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\label{tab:operations}
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\end{table}
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\section{Instruction Encoding}
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All instructions are 32-bits wide, and start with a 4-bit condition
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code and 6-bit opcode. The rest of the instruction is used for
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operands, and is dependent upon the addressing mode.
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Registers are always referenced by a 5-bit register number. Signed
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immediate values have a sign bit in the most significant position (1
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indicating negative).
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\begin{figure}[h]
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\centering
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\begin{tabularx}{\textwidth}{|*{32}{@{}B@{}|}}
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\hline
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31 & 30 & 29 & 28 & 27 & 26 & 25 & 24 & 23 & 22 & 21 & 20 & 19 &
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18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 &
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4 & 3 & 2 & 1 & 0 \\
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\hline
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\multicolumn{4}{|l|}{Cond.} &
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\multicolumn{6}{l|}{Opcode} &
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\multicolumn{22}{l|}{\textit{Operands}} \\
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\hline
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\end{tabularx}
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\caption{Instruction encoding}
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\label{fig:instruction-encoding}
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\end{figure}
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\begin{figure}[h]
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\centering
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\begin{tabularx}{\textwidth}{c|*{23}{@{}B@{}|}}
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\cline{2-23}
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& 21 & 20 & 19 & 18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 &
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8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
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\hline
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\multicolumn{1}{|c|}{\texttt{RD}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{src1}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{src2}}} &
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\multicolumn{7}{l|}{\textit{Unused}} \\
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\hline
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\multicolumn{1}{|c|}{\texttt{RI}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{src}}} &
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\multicolumn{12}{l|}{Signed 12-bit immediate} \\
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\hline
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\multicolumn{1}{|c|}{\texttt{BO}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{base}}} &
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\multicolumn{12}{l|}{
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\texttt{I\textsubscript{offset}} (Unsigned 12-bit immediate)} \\
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\hline
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\multicolumn{1}{|c|}{\texttt{BI}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{base}}} &
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\multicolumn{5}{l|}{\texttt{R\textsubscript{index}}} &
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\multicolumn{7}{l|}{\textit{Unused}} \\
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\hline
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\multicolumn{1}{|c|}{\texttt{I}} &
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\multicolumn{22}{l|}{Signed 22-bit immediate} \\
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\hline
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\end{tabularx}
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\caption{Operand encodings for the different address modes}
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\label{fig:operand-encoding}
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\end{figure}
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\end{document}
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