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\documentclass[a4paper]{article}
\usepackage{array}
\usepackage{graphicx}
\usepackage[utf8]{inputenc}
\usepackage{multirow}
\usepackage{nameref}
\usepackage{parskip}
\usepackage{tabularx}
\newcolumntype{B}{>{\centering\tiny\bfseries\arraybackslash}X}
\newcommand{\noopcode}{\multicolumn{1}{c|}{--}}
\newcommand{\op}[1]{\texttt{#1}}
\newcommand{\opsep}{\cline{2-8} \multicolumn{1}{|c|}{}}
\newcommand{\opfamily}[2]{
\hline\multicolumn{1}{|c|}{\multirow{#1}{*}{\rotatebox{90}{\textbf{#2}}}}}
\title{ETD32 ISA Specification}
\author{Camden Dixie O'Brien}
\begin{document}
\maketitle
The ETD32 ISA is a little-endian, 32-bit RISC architecture, primarily
designed to be simple and relatively easy to implement for teaching
processor internals and design.
\section{Registers}
\begin{table}[h]
\centering
\begin{tabularx}{\textwidth}{|l|r|X|}
\hline
\textbf{Name} & \textbf{Number} & \textbf{Purpose} \\
\hline
Z & 0 & ``Black hole'' pseudo-register \\
\hline
R1--R29 & 1--29 & General purpose \\
\hline
SP & 30 & Stack pointer \\
\hline
PC & 31 & Program counter \\
\hline
\end{tabularx}
\caption{List of Registers}
\end{table}
There are a total of 32 directly addressable registers. They are
uniquely identified by their 5-bit register number.
In addition to these, there is a flags register which cannot be
addressed directly, but affects conditional execution of commands; see
section \ref{sec:conditional-execution} for more details.
\section{Addressing Modes}
\subsection{Register Direct (\texttt{RD})}
\begin{center}
\texttt{Op R\textsubscript{dest},R\textsubscript{src1},R\textsubscript{src2}}
\end{center}
In register direct mode, the operands consist of up to three register
numbers. The first register is always a destination; if the second and
third are present they are used as sources.
\subsection{Register-Immediate (\texttt{RI})}
\begin{center}
\texttt{Op R\textsubscript{dest},R\textsubscript{src},\#I}
\end{center}
Register-immediate instructions have a destination register and a
single source register, with the rest of the instruction being a
signed, 12-bit immediate value.
\subsection{Base-Offset (\texttt{BO})}
\begin{center}
\texttt{
Op R\textsubscript{target},[R\textsubscript{base},\#I\textsubscript{offset}]}
\end{center}
Base-offset addressing uses a target register, which may be used as
input or output depending on the operation, a base register and a
12-bit immediate value (the offset). The offset is added to the value
of the base register, and this is used as a memory address.
\subsection{Base-Index (\texttt{BI})}
\begin{center}
\texttt{
Op R\textsubscript{target},[R\textsubscript{base},R\textsubscript{index}]}
\end{center}
Base-index addressing is similar to base-offset addressing, except an
index register is provided instead of an offset immediate. The values
of the base and index registers are added together and used as a
memory address.
\subsection{Immediate-Only (\texttt{I})}
\begin{center}
\texttt{Op \#I}
\end{center}
The simplest addressing mode; immediate-only instructions specify a
single, signed, 22-bit immediate value.
\section{Conditional Execution}
\label{sec:conditional-execution}
Many instructions set the condition flags, which are stored in the
(not directly addressable) flags register. Any flags that are not set
by an operation are implicitly cleared.
\begin{table}[h]
\centering
\begin{tabularx}{\textwidth}{|c|X|}
\hline
\textbf{Flag} & \textbf{Description} \\
\hline
C & Carry / overflow \\
\hline
N & Less than zero \\
\hline
Z & Equal to zero \\
\hline
P & Greater than zero \\
\hline
\end{tabularx}
\caption{Condition flags}
\label{tab:condition-flags}
\end{table}
All instructions can be conditionally executed depending on any
combination of the four condition flags in the flag register. This is
denoted by appending a question mark (`?') and the character codes of
all flags that should be depended on to the opcode. For example, a
suffix of \texttt{?NP} would indicate that the instruction should only
be executed if the \texttt{N} and \texttt{P} flags are both set---that
is, if the previous command yielded a value that was not equal to
zero.
\section{Operations}
There are a total of 18 distinct operations, with 33 opcodes (each
addressing mode variant of a command has its own opcode). They fall
into three categories: \textbf{Logic \& Arithmetic}, \textbf{Memory}
and \textbf{Flow Control}.
Refer to table \ref{tab:operations} for an exhaustive list of these
operations and their opcodes.
\begin{table}[p]
\begin{tabularx}{\textwidth}{cl|*{5}{r|}X|}
\cline{3-8}
& &
\multicolumn{5}{c|}{\textbf{Opcode}} &
\multirow{2}{*}{\textbf{Description}} \\
\cline{3-7}
&
& \multicolumn{1}{c|}{\texttt{RD}} & \multicolumn{1}{c|}{\texttt{RI}}
& \multicolumn{1}{c|}{\texttt{BO}} & \multicolumn{1}{c|}{\texttt{BI}}
& \multicolumn{1}{c|}{\texttt{I}} & \\
\opfamily{14}{Logic \& Arithmetic} &
\op{LLS} & 0 & 1 & \noopcode & \noopcode & \noopcode &
Applies a logical left shift to its first input; the second input
determines the number of places \\
\opsep &
\op{LRS} & 2 & 3 & \noopcode & \noopcode & \noopcode &
Logical right shift; otherwise the same as \texttt{LLS} \\
\opsep &
\op{AND} & 4 & 5 & \noopcode & \noopcode & \noopcode &
Bitwise \texttt{AND}s its inputs \\
\opsep &
\op{OR} & 6 & 7 & \noopcode & \noopcode & \noopcode &
Bitwise \texttt{OR}s its inputs \\
\opsep &
\op{XOR} & 8 & 9 & \noopcode & \noopcode & \noopcode &
Bitwise \texttt{XOR}s its inputs \\
\opsep &
\op{NOT} & 10 & \noopcode & \noopcode & \noopcode & \noopcode &
Bitwise \texttt{NOT}s its first input. The second input is ignored. \\
\opsep &
\op{ADD} & 11 & 12 & \noopcode & \noopcode & \noopcode &
Adds its inputs \\
\opsep &
\op{SUB} & 13 & 14 & \noopcode & \noopcode & \noopcode &
Subtracts its second input from its first (two's complement) \\
\opsep &
\op{MUL} & 15 & 16 & \noopcode & \noopcode & \noopcode &
Multiplies its inputs \\
\opfamily{10}{Memory} &
\op{LD8} & \noopcode & \noopcode & 17 & 18 & \noopcode &
Loads a byte from the address in memory and writes it to the
target register \\
\opsep & \op{LD16} & \noopcode & \noopcode & 19 & 20 & \noopcode &
Same as \texttt{LD8}, but a half-word \\
\opsep & \op{LD32} & \noopcode & \noopcode & 21 & 22 & \noopcode &
Same as \texttt{LD16}, but a full word \\
\opsep &
\op{ST8} & \noopcode & \noopcode & 23 & 24 & \noopcode &
Writes the least-significant byte of the contents of the target register
to the memory address \\
\opsep &
\op{ST16} & \noopcode & \noopcode & 25 & 26 & \noopcode &
Same as \texttt{ST8} but a half-word \\
\opsep &
\op{ST16} & \noopcode & \noopcode & 27 & 28 & \noopcode &
Same as \texttt{ST8} but a full word \\
\opfamily{7}{Flow control} &
\op{B} & \noopcode & \noopcode & \noopcode & \noopcode & 29 &
Jump to the given offset from the PC; argument must be a multiple of 4 \\
\opsep &
\op{JMP} & 30 & \noopcode & \noopcode & \noopcode & 31 &
Jump to the given address; must be word-aligned. For the \texttt{RD}
variant, only the first source register is used. \\
\opsep &
\op{TI} & \noopcode & \noopcode & \noopcode & \noopcode & 32 &
Trigger a software interrupt; the argument is ignored \\
\hline
\end{tabularx}
\caption{List of Operations}
\label{tab:operations}
\end{table}
\section{Instruction Encoding}
All instructions are 32-bits wide, and start with a 4-bit condition
code and 6-bit opcode. The rest of the instruction is used for
operands, and is dependent upon the addressing mode.
Registers are always referenced by a 5-bit register number. Signed
immediate values have a sign bit in the most significant position (1
indicating negative).
\begin{figure}[h]
\centering
\begin{tabularx}{\textwidth}{|*{32}{@{}B@{}|}}
\hline
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24 & 23 & 22 & 21 & 20 & 19 &
18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 &
4 & 3 & 2 & 1 & 0 \\
\hline
\multicolumn{4}{|l|}{Cond.} &
\multicolumn{6}{l|}{Opcode} &
\multicolumn{22}{l|}{\textit{Operands}} \\
\hline
\end{tabularx}
\caption{Instruction encoding}
\label{fig:instruction-encoding}
\end{figure}
\begin{figure}[h]
\centering
\begin{tabularx}{\textwidth}{c|*{23}{@{}B@{}|}}
\cline{2-23}
& 21 & 20 & 19 & 18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 &
8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
\hline
\multicolumn{1}{|c|}{\texttt{RD}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src1}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src2}}} &
\multicolumn{7}{l|}{\textit{Unused}} \\
\hline
\multicolumn{1}{|c|}{\texttt{RI}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src}}} &
\multicolumn{12}{l|}{Signed 12-bit immediate} \\
\hline
\multicolumn{1}{|c|}{\texttt{BO}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{base}}} &
\multicolumn{12}{l|}{
\texttt{I\textsubscript{offset}} (Unsigned 12-bit immediate)} \\
\hline
\multicolumn{1}{|c|}{\texttt{BI}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{base}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{index}}} &
\multicolumn{7}{l|}{\textit{Unused}} \\
\hline
\multicolumn{1}{|c|}{\texttt{I}} &
\multicolumn{22}{l|}{Signed 22-bit immediate} \\
\hline
\end{tabularx}
\caption{Operand encodings for the different address modes}
\label{fig:operand-encoding}
\end{figure}
\end{document}