cdo/etd32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix some issues and tweak some phrasing

Browse Source 
- Tweak and fix typo in operations table
- Restructure encoding section a little, add more information about
  condition codes
- Specify condition code structure in instruction encoding figure
- Tweak addressing mode notation
- Add a little more to intro paragraph
- Rephrase some address mode descriptions
- Rephrase registers and condition execution sections a little
- Use italics instead of bold for emphasis
- Add more information about Z register
- Remove '?' from condition code suffix
This commit is contained in:
Camden Dixie O'Brien 2023-10-05 15:29:20 +01:00
parent 6463d51a5f
commit a810f9145f
1 changed files with 56 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

99
spec.tex
View File

@ -57,12 +57,18 @@
\maketitle \maketitle
The ETD32 ISA is a little-endian, 32-bit RISC architecture, primarily The ETD32 ISA is a little-endian, 32-bit RISC architecture, designed
designed to be simple and relatively easy to implement for teaching to be simple and relatively easy to implement. It is primarily
processor internals and design. intended for educational use, such as teaching processor internals and
design, assembly language programming and compiler development.
\section{Registers} \section{Registers}
There are a total of 32 directly addressable registers, which are
uniquely identified by their 5-bit register number. The Z register
(register number 0) is a special ``black hole'' register: any writes
to this register have no effect and when read it always yields zero.
\begin{table}[h] \begin{table}[h]
\centering \centering
\begin{tabular}{lrl} \begin{tabular}{lrl}
@ -78,11 +84,8 @@ processor internals and design.
\caption{List of Registers} \caption{List of Registers}
\end{table} \end{table}
There are a total of 32 directly addressable registers. They are
uniquely identified by their 5-bit register number.
In addition to these, there is a flags register which cannot be In addition to these, there is a flags register which cannot be
addressed directly, but affects conditional execution of commands; see addressed directly but affects conditional execution of commands. See
section \ref{sec:conditional-execution} for more details. section \ref{sec:conditional-execution} for more details.
\section{Addressing Modes} \section{Addressing Modes}
@ -90,17 +93,17 @@ section \ref{sec:conditional-execution} for more details.
\subsection{Register Direct (RD)} \subsection{Register Direct (RD)}
\begin{center} \begin{center}
\texttt{Op R\textsubscript{dest},R\textsubscript{src1},R\textsubscript{src2}} \texttt{Op R\textsubscript{dest},R\textsubscript{x},R\textsubscript{y}}
\end{center} \end{center}
In register direct mode, the operands consist of up to three register In register direct mode, the operands consist of up to three register
numbers. The first register is always a destination; if the second and numbers. The first register is a destination; the second and third are
third are present they are used as sources. inputs.
\subsection{Register-Immediate (RI)} \subsection{Register-Immediate (RI)}
\begin{center} \begin{center}
\texttt{Op R\textsubscript{dest},R\textsubscript{src},\#I} \texttt{Op R\textsubscript{dest},R\textsubscript{x},\#I\textsubscript{y}}
\end{center} \end{center}
Register-immediate instructions have a destination register and a Register-immediate instructions have a destination register and a
@ -114,8 +117,8 @@ signed, 12-bit immediate value.
Op R\textsubscript{target},[R\textsubscript{base},\#I\textsubscript{offset}]} Op R\textsubscript{target},[R\textsubscript{base},\#I\textsubscript{offset}]}
\end{center} \end{center}
Base-offset addressing uses a target register, which may be used as Base-offset addressing uses a target register---which may be used as
input or output depending on the operation, a base register and a input or output depending on the operation---a base register and a
12-bit immediate value (the offset). The offset is added to the value 12-bit immediate value (the offset). The offset is added to the value
of the base register, and this is used as a memory address. of the base register, and this is used as a memory address.
@ -143,9 +146,10 @@ signed, 22-bit immediate value.
\section{Conditional Execution} \section{Conditional Execution}
\label{sec:conditional-execution} \label{sec:conditional-execution}
Many instructions set the condition flags, which are stored in the Instructions which yield a value (logic and arithmetic or memory load
(not directly addressable) flags register. Any flags that are not set operations) set the condition flags, which are stored in the flags
by an operation are implicitly cleared. register. Any flags that are not set by an operation are implicitly
cleared.
\begin{table}[h] \begin{table}[h]
\centering \centering
@ -165,26 +169,26 @@ by an operation are implicitly cleared.
All instructions can be conditionally executed depending on any All instructions can be conditionally executed depending on any
combination of the four condition flags in the flag register. This is combination of the four condition flags in the flag register. This is
denoted by appending a question mark (`?') and the character codes of conventionally denoted by appending the character codes of all flags
all flags that should be depended on to the opcode. For example, a that should be depended on to the mnemonic. For example, a suffix of
suffix of \texttt{?NP} would indicate that the instruction should only \texttt{NP} would indicate that the instruction should only be
be executed if the \texttt{N} and \texttt{P} flags are both set---that executed if the \texttt{N} and \texttt{P} flags are both set---that
is, if the previous command yielded a value that was not equal to is, if the previous command yielded a value that was not equal to
zero. zero.
\section{Operations} \section{Instruction Set}
There are a total of 18 distinct operations, with 33 opcodes (each There are a total of 18 distinct operations, with 33 opcodes (each
addressing mode variant of a command has its own opcode). They fall addressing mode variant of a command has its own opcode). They fall
into three categories: \textbf{Logic \& Arithmetic}, \textbf{Memory} into three categories: \emph{Logic \& Arithmetic}, \emph{Memory}
and \textbf{Flow Control}. Refer to table \ref{tab:operations} for an and \emph{Flow Control}. Refer to table \ref{tab:operations} for an
exhaustive list of these operations and their opcodes. exhaustive list of these operations and their opcodes.
\begin{table}[p] \begin{table}[p]
\renewcommand{\arraystretch}{1.2} \renewcommand{\arraystretch}{1.2}
\begin{tabularx}{\textwidth}{cl*{5}{r}X} \begin{tabularx}{\textwidth}{cl*{5}{r}X}
\toprule \toprule
\multicolumn{2}{c}{\multirow{2}{*}{\textbf{Op}}} & \multicolumn{2}{c}{\multirow{2}{*}{\textbf{Operation}}} &
\multicolumn{5}{c}{\textbf{Opcode}} & \multicolumn{5}{c}{\textbf{Opcode}} &
\multirow{2}{*}{\textbf{Description}} \\ \multirow{2}{*}{\textbf{Description}} \\
\cmidrule(r){3-7} \cmidrule(r){3-7}
@ -193,7 +197,7 @@ exhaustive list of these operations and their opcodes.
& \multicolumn{1}{c}{BO} & \multicolumn{1}{c}{BI} & \multicolumn{1}{c}{BO} & \multicolumn{1}{c}{BI}
& \multicolumn{1}{c}{I} & \\ & \multicolumn{1}{c}{I} & \\
\opfamily{14}{Logic \& Arithmetic} & \opfamily{13}{Logic \& Arithmetic} &
\op{LLS} & 0 & 1 & \noopcode & \noopcode & \noopcode & \op{LLS} & 0 & 1 & \noopcode & \noopcode & \noopcode &
Applies a logical left shift to its first input; the second input Applies a logical left shift to its first input; the second input
determines the number of places \\ determines the number of places \\
@ -230,7 +234,7 @@ exhaustive list of these operations and their opcodes.
\op{MUL} & 15 & 16 & \noopcode & \noopcode & \noopcode & \op{MUL} & 15 & 16 & \noopcode & \noopcode & \noopcode &
Multiplies its inputs \\ Multiplies its inputs \\
\opfamily{10}{Memory} & \opfamily{9.3}{Memory} &
\op{LD8} & \noopcode & \noopcode & 17 & 18 & \noopcode & \op{LD8} & \noopcode & \noopcode & 17 & 18 & \noopcode &
Loads a byte from the address in memory and writes it to the Loads a byte from the address in memory and writes it to the
target register \\ target register \\
@ -239,7 +243,7 @@ exhaustive list of these operations and their opcodes.
Same as \texttt{LD8}, but a half-word \\ Same as \texttt{LD8}, but a half-word \\
\opsep & \op{LD32} & \noopcode & \noopcode & 21 & 22 & \noopcode & \opsep & \op{LD32} & \noopcode & \noopcode & 21 & 22 & \noopcode &
Same as \texttt{LD16}, but a full word \\ Same as \texttt{LD8}, but a full word \\
\opsep & \opsep &
\op{ST8} & \noopcode & \noopcode & 23 & 24 & \noopcode & \op{ST8} & \noopcode & \noopcode & 23 & 24 & \noopcode &
@ -251,10 +255,10 @@ exhaustive list of these operations and their opcodes.
Same as \texttt{ST8} but a half-word \\ Same as \texttt{ST8} but a half-word \\
\opsep & \opsep &
\op{ST16} & \noopcode & \noopcode & 27 & 28 & \noopcode & \op{ST32} & \noopcode & \noopcode & 27 & 28 & \noopcode &
Same as \texttt{ST8} but a full word \\ Same as \texttt{ST8} but a full word \\
\opfamily{7}{Flow control} & \opfamily{6.3}{Flow control} &
\op{B} & \noopcode & \noopcode & \noopcode & \noopcode & 29 & \op{B} & \noopcode & \noopcode & \noopcode & \noopcode & 29 &
Jump to the given offset from the PC; argument must be a multiple of 4 \\ Jump to the given offset from the PC; argument must be a multiple of 4 \\
@ -274,13 +278,12 @@ exhaustive list of these operations and their opcodes.
\section{Instruction Encoding} \section{Instruction Encoding}
All instructions are 32-bits wide, and start with a 4-bit condition All instructions are 32-bits wide and have a 4-bit condition code in
code and 6-bit opcode. The rest of the instruction is used for the most-significant position, directly followed by a 6-bit
operands, and is dependent upon the addressing mode. opcode. Each bit in the condition code corresponds to one of the flags
(see figure \ref{fig:instruction-encoding} for the order); the bit
Registers are always referenced by a 5-bit register number. Signed being set indicates that execution of the command should depend on the
immediate values have a sign bit in the most significant position (1 corresponding flag being set.
indicating negative).
\begin{figure}[h] \begin{figure}[h]
\renewcommand{\arraystretch}{1.2} \renewcommand{\arraystretch}{1.2}
@ -291,7 +294,10 @@ indicating negative).
18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 & 18 & 17 & 16 & 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 &
4 & 3 & 2 & 1 & 0 \\ 4 & 3 & 2 & 1 & 0 \\
\hline \hline
\multicolumn{4}{|l|}{Cond.} & \multicolumn{1}{|@{}c@{}|}{C} &
\multicolumn{1}{@{}c@{}|}{N} &
\multicolumn{1}{@{}c@{}|}{Z} &
\multicolumn{1}{@{}c@{}|}{P} &
\multicolumn{6}{l|}{Opcode} & \multicolumn{6}{l|}{Opcode} &
\multicolumn{22}{l|}{\textit{Operands}} \\ \multicolumn{22}{l|}{\textit{Operands}} \\
\hline \hline
@ -300,6 +306,12 @@ indicating negative).
\label{fig:instruction-encoding} \label{fig:instruction-encoding}
\end{figure} \end{figure}
The rest of the instruction is used for operands. Registers are always
referenced by a 5-bit register number. Signed immediate values have a
sign bit in the most significant position, with 1 indicating a
negative value. The specific encoding depends upon the addressing
mode; these encodings are shown in figure \ref{fig:operand-encodings}.
\begin{figure}[h] \begin{figure}[h]
\renewcommand{\arraystretch}{1.2} \renewcommand{\arraystretch}{1.2}
\centering \centering
@ -310,14 +322,15 @@ indicating negative).
\hline \hline
\multicolumn{1}{|r|}{RD} & \multicolumn{1}{|r|}{RD} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src1}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{x}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src2}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{y}}} &
\multicolumn{7}{l|}{\textit{Unused}} \\ \multicolumn{7}{l|}{\textit{Unused}} \\
\hline \hline
\multicolumn{1}{|r|}{RI} & \multicolumn{1}{|r|}{RI} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{dest}}} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{src}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{x}}} &
\multicolumn{12}{l|}{Signed 12-bit immediate} \\ \multicolumn{12}{l|}{
\texttt{I\textsubscript{y}} (Signed 12-bit immediate)} \\
\hline \hline
\multicolumn{1}{|r|}{BO} & \multicolumn{1}{|r|}{BO} &
\multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} & \multicolumn{5}{l|}{\texttt{R\textsubscript{target}}} &
@ -332,11 +345,11 @@ indicating negative).
\multicolumn{7}{l|}{\textit{Unused}} \\ \multicolumn{7}{l|}{\textit{Unused}} \\
\hline \hline
\multicolumn{1}{|r|}{I} & \multicolumn{1}{|r|}{I} &
\multicolumn{22}{l|}{Signed 22-bit immediate} \\ \multicolumn{22}{l|}{\texttt{I} (Signed 22-bit immediate)} \\
\hline \hline
\end{tabularx} \end{tabularx}
\caption{Operand encodings for the different address modes} \caption{Operand encodings for the different address modes}
\label{fig:operand-encoding} \label{fig:operand-encodings}
\end{figure} \end{figure}
\end{document} \end{document}