From b1d6ad2ace2f3341f8d50fa59d7df61cba428d39 Mon Sep 17 00:00:00 2001 From: Camden Dixie O'Brien Date: Sat, 9 Nov 2024 11:52:18 +0000 Subject: [PATCH] Use multicols instead of twocolumn and adjust margins --- main.tex | 262 ++++++++++++++++++++++++++++--------------------------- 1 file changed, 134 insertions(+), 128 deletions(-) diff --git a/main.tex b/main.tex index 80f036b..a57c1c3 100644 --- a/main.tex +++ b/main.tex @@ -1,11 +1,13 @@ -\documentclass[a4paper,twocolumn]{article} +\documentclass[a4paper]{article} \usepackage{booktabs} \usepackage{baskervald} \usepackage{courierten} \usepackage{cuted} +\usepackage[hmargin=2.5cm,vmargin=3.5cm]{geometry} \usepackage{helvet} \usepackage{mathtools} +\usepackage{multicol} \usepackage{sectsty} \usepackage{tabularx} @@ -16,136 +18,140 @@ \begin{document} -\begin{strip} - \centering \LARGE \bfseries AMD64 Cheatsheet +\begin{center} + \LARGE \bfseries AMD64 Cheatsheet \vspace{1em} -\end{strip} - -\newlength{\colwidth} -\setlength{\colwidth}{\linewidth} -\addtolength{\colwidth}{-0.5\columnsep} - -\section{Instructions} - -\noindent\begin{tabularx}{\colwidth}{>{\ttfamily}l>{\ttfamily}l>{$}X<{$}} - \toprule - \multicolumn{3}{>{\sffamily\bfseries}c}{Arithmetic \& Logic} \\ - \midrule - add & S,D & D \leftarrow S + D \\ - sub & S,D & D \leftarrow D - S \\ - neg & D & D \leftarrow -D \\ - inc & D & D \leftarrow D + 1 \\ - dec & D & D \leftarrow D - 1 \\ - imul & S,D & D \leftarrow S \times D \\ - idiv & S & \mathtt{rax} \leftarrow \lfloor\mathtt{rdx}:\mathtt{rax} \div S\rfloor \\ - & & \mathtt{rdx} \leftarrow (\mathtt{rdx}:\mathtt{rax})\mod{S} \\ - and & S,D & D \leftarrow S \mathbin{\&} D \\ - or & S,D & D \leftarrow S \mathbin{|} D \\ - xor & S,D & D \leftarrow S \wedge D \\ - not & D & D \leftarrow \mathord{\sim} D \\ - sal & n,D & D \leftarrow D \ll n \\ - shr & n,D & D \leftarrow D \gg n \hspace{1em} \textrm{(logical)} \\ - sar & n,D & D \leftarrow D \gg n \hspace{1em} \textrm{(arithmetic)} \\ - \midrule - \multicolumn{3}{>{\sffamily\bfseries}c}{Data transfer} \\ - \midrule - lea & S,D & D \leftarrow \mathrm{addressof}(S) \\ - mov & S,D & D \leftarrow S \\ - \midrule - \multicolumn{3}{>{\sffamily\bfseries}c}{Conditionals \& Branches} \\ - \midrule - cmp & A,B & B - A \hspace{1em} \textrm{(setting cond. flags)} \\ - test & A,B & A \mathbin{\&} B \hspace{1em} \textrm{(setting cond. flags)} \\ - jmp & l & \textrm{jump to \texttt{l} unconditionally} \\ - je & l & \textrm{jump to \texttt{l} if equal} \\ - jne & l & \textrm{jump to \texttt{l} if not equal} \\ - js & l & \textrm{jump to \texttt{l} if negative} \\ - jns & l & \textrm{jump to \texttt{l} if non-negative} \\ - jg & l & \textrm{jump to \texttt{l} if greater} \\ - jge & l & \textrm{jump to \texttt{l} if greater or equal} \\ - jl & l & \textrm{jump to \texttt{l} if lesser} \\ - jle & l & \textrm{jump to \texttt{l} if lesser or equal} \\ - ja & l & \textrm{jump to \texttt{l} if above} \\ - jae & l & \textrm{jump to \texttt{l} if above or equal} \\ - jb & l & \textrm{jump to \texttt{l} if below} \\ - jbe & l & \textrm{jump to \texttt{l} if below or equal} \\ - \midrule - \multicolumn{3}{>{\sffamily\bfseries}c}{Stack operations} \\ - \midrule - push & S & \mathtt{rsp} \leftarrow \mathtt{rsp} - \mathrm{sizeof}(S) \\ - & & \mathrm{at}(\mathtt{rsp}) \leftarrow S \\ - pop & D & D \leftarrow \mathrm{at}(\mathtt{rsp}) \\ - & & \mathtt{rsp} \leftarrow \mathtt{rsp} + \mathrm{sizeof}(S) \\ - callq & l & \textrm{push \texttt{rip} then jump to \texttt{l}} \\ - retq & & \textrm{pop to \texttt{rip}} \\ - \bottomrule -\end{tabularx} - -\noindent\begin{tabularx}{\colwidth}{lX} - \toprule - \multicolumn{2}{>{\sffamily\bfseries}c}{Addressing Modes} \\ - \midrule - Immediate & \texttt{\$C} \\ - Register & \texttt{\%R} \\ - Memory & \texttt{[C\textsubscript{d}](\%R\textsubscript{b}[,\%R\textsubscript{i}[,C\textsubscript{s}])} \\ - \bottomrule -\end{tabularx} - -\[\textrm{Memory Address} = C_d + R_b + C_sR_i\] - -\noindent\begin{center} - \begin{tabular}{cl} - \toprule - \multicolumn{2}{>{\sffamily\bfseries}c}{Suffixes} \\ - \midrule - b & 8 bits \\ - w & 16 bits \\ - l & 32 bits \\ - q & 64 bits \\ - \bottomrule - \end{tabular} - \hspace{1em} - \begin{tabular}{cl} - \toprule - \multicolumn{2}{>{\sffamily\bfseries}c}{Condition Flags} \\ - \midrule - ZF & Zero \\ - SF & Sign (set on negative) \\ - CF & Carry \\ - OF & Overflow \\ - \bottomrule - \end{tabular} \end{center} -\section{Registers} +\begin{multicols}{2} -\begin{tabularx}{\colwidth}{>{\ttfamily}c>{\ttfamily}c>{\ttfamily}c>{\ttfamily}cX} - \toprule - \multicolumn{5}{>{\sffamily\bfseries}c}{Standard} \\ - \midrule - rax & eax & ax & al & Accumulator \\ - rbx & ebx & bx & bl & DS data pointer \\ - rcx & ecx & cx & cl & Counter \\ - rdx & edx & dx & dl & I/O pointer \\ - rsi & esi & si & sil & Source pointer \\ - rdi & edi & di & dil & Dest. pointer \\ - \midrule - \multicolumn{5}{>{\sffamily\bfseries}c}{Stack} \\ - \midrule - rsp & esp & sp & spl & Stack pointer \\ - rbp & ebp & bp & bpl & Base pointer \\ - \midrule - \multicolumn{5}{>{\sffamily\bfseries}c}{64-bit Mode Only} \\ - \midrule - r8 & r8d & r8w & r8b & No special use \\ - r9 & r9d & r9w & r9b & \\ - r10 & r10d & r10w & r10b & \\ - r11 & r11d & r11w & r11b & \\ - r12 & r12d & r12w & r12b & \\ - r13 & r13d & r13w & r13b & \\ - r14 & r14d & r14w & r14b & \\ - r15 & r15d & r15w & r15b & \\ - \bottomrule -\end{tabularx} + \newlength{\colwidth} + \setlength{\colwidth}{\linewidth} + \addtolength{\colwidth}{-0.5\columnsep} + + \section{Instructions} + + \noindent\begin{tabularx}{\colwidth}{>{\ttfamily}l>{\ttfamily}l>{$}X<{$}} + \toprule + \multicolumn{3}{>{\sffamily\bfseries}c}{Arithmetic \& Logic} \\ + \midrule + add & S,D & D \leftarrow S + D \\ + sub & S,D & D \leftarrow D - S \\ + neg & D & D \leftarrow -D \\ + inc & D & D \leftarrow D + 1 \\ + dec & D & D \leftarrow D - 1 \\ + imul & S,D & D \leftarrow S \times D \\ + idiv & S & \mathtt{rax} \leftarrow \lfloor\mathtt{rdx}:\mathtt{rax} \div S\rfloor \\ + & & \mathtt{rdx} \leftarrow (\mathtt{rdx}:\mathtt{rax})\mod{S} \\ + and & S,D & D \leftarrow S \mathbin{\&} D \\ + or & S,D & D \leftarrow S \mathbin{|} D \\ + xor & S,D & D \leftarrow S \wedge D \\ + not & D & D \leftarrow \mathord{\sim} D \\ + sal & n,D & D \leftarrow D \ll n \\ + shr & n,D & D \leftarrow D \gg n \hspace{1em} \textrm{(logical)} \\ + sar & n,D & D \leftarrow D \gg n \hspace{1em} \textrm{(arithmetic)} \\ + \midrule + \multicolumn{3}{>{\sffamily\bfseries}c}{Data transfer} \\ + \midrule + lea & S,D & D \leftarrow \mathrm{addressof}(S) \\ + mov & S,D & D \leftarrow S \\ + \midrule + \multicolumn{3}{>{\sffamily\bfseries}c}{Conditionals \& Branches} \\ + \midrule + cmp & A,B & B - A \hspace{1em} \textrm{(setting cond. flags)} \\ + test & A,B & A \mathbin{\&} B \hspace{1em} \textrm{(setting cond. flags)} \\ + jmp & l & \textrm{jump to \texttt{l} unconditionally} \\ + je & l & \textrm{jump to \texttt{l} if equal} \\ + jne & l & \textrm{jump to \texttt{l} if not equal} \\ + js & l & \textrm{jump to \texttt{l} if negative} \\ + jns & l & \textrm{jump to \texttt{l} if non-negative} \\ + jg & l & \textrm{jump to \texttt{l} if greater} \\ + jge & l & \textrm{jump to \texttt{l} if greater or equal} \\ + jl & l & \textrm{jump to \texttt{l} if lesser} \\ + jle & l & \textrm{jump to \texttt{l} if lesser or equal} \\ + ja & l & \textrm{jump to \texttt{l} if above} \\ + jae & l & \textrm{jump to \texttt{l} if above or equal} \\ + jb & l & \textrm{jump to \texttt{l} if below} \\ + jbe & l & \textrm{jump to \texttt{l} if below or equal} \\ + \midrule + \multicolumn{3}{>{\sffamily\bfseries}c}{Stack operations} \\ + \midrule + push & S & \mathtt{rsp} \leftarrow \mathtt{rsp} - \mathrm{sizeof}(S) \\ + & & \mathrm{at}(\mathtt{rsp}) \leftarrow S \\ + pop & D & D \leftarrow \mathrm{at}(\mathtt{rsp}) \\ + & & \mathtt{rsp} \leftarrow \mathtt{rsp} + \mathrm{sizeof}(S) \\ + callq & l & \textrm{push \texttt{rip} then jump to \texttt{l}} \\ + retq & & \textrm{pop to \texttt{rip}} \\ + \bottomrule + \end{tabularx} + + \noindent\begin{tabularx}{\colwidth}{lX} + \toprule + \multicolumn{2}{>{\sffamily\bfseries}c}{Addressing Modes} \\ + \midrule + Immediate & \texttt{\$C} \\ + Register & \texttt{\%R} \\ + Memory & \texttt{[C\textsubscript{d}](\%R\textsubscript{b}[,\%R\textsubscript{i}[,C\textsubscript{s}])} \\ + \bottomrule + \end{tabularx} + + \[\textrm{Memory Address} = C_d + R_b + C_sR_i\] + + \noindent\begin{center} + \begin{tabular}{cl} + \toprule + \multicolumn{2}{>{\sffamily\bfseries}c}{Suffixes} \\ + \midrule + b & 8 bits \\ + w & 16 bits \\ + l & 32 bits \\ + q & 64 bits \\ + \bottomrule + \end{tabular} + \hspace{1em} + \begin{tabular}{cl} + \toprule + \multicolumn{2}{>{\sffamily\bfseries}c}{Condition Flags} \\ + \midrule + ZF & Zero \\ + SF & Sign (set on negative) \\ + CF & Carry \\ + OF & Overflow \\ + \bottomrule + \end{tabular} + \end{center} + + \section{Registers} + + \begin{tabularx}{\colwidth}{>{\ttfamily}c>{\ttfamily}c>{\ttfamily}c>{\ttfamily}cX} + \toprule + \multicolumn{5}{>{\sffamily\bfseries}c}{Standard} \\ + \midrule + rax & eax & ax & al & Accumulator \\ + rbx & ebx & bx & bl & DS data pointer \\ + rcx & ecx & cx & cl & Counter \\ + rdx & edx & dx & dl & I/O pointer \\ + rsi & esi & si & sil & Source pointer \\ + rdi & edi & di & dil & Dest. pointer \\ + \midrule + \multicolumn{5}{>{\sffamily\bfseries}c}{Stack} \\ + \midrule + rsp & esp & sp & spl & Stack pointer \\ + rbp & ebp & bp & bpl & Base pointer \\ + \midrule + \multicolumn{5}{>{\sffamily\bfseries}c}{64-bit Mode Only} \\ + \midrule + r8 & r8d & r8w & r8b & No special use \\ + r9 & r9d & r9w & r9b & \\ + r10 & r10d & r10w & r10b & \\ + r11 & r11d & r11w & r11b & \\ + r12 & r12d & r12w & r12b & \\ + r13 & r13d & r13w & r13b & \\ + r14 & r14d & r14w & r14b & \\ + r15 & r15d & r15w & r15b & \\ + \bottomrule + \end{tabularx} + +\end{multicols} \end{document}